Publications
Patents, papers and other publications authored/co-authored by Vikas.
Publication - Method of Testing Shared Caches/TLB Intervention
A method for testing coherency in shared caches and TLB subsystem with true sharing as the underlying stress mechanism.
April 2015
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Publication - Automated Electrical Validation of Microprocessor and Shared Memory Subsystem
A method for automated electrical testing of microprocessor subsystem using serveral types of memory bist patterns.
July 2014
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Patent - Method of testing coherency of data storage in multi-processor shared memory system
A method for testing coherency in shared caches and TLBs with false sharing & tlb thrashing as the underlying stress mechanisms.
February 2014
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© 2020 Vikas Chouhan