A memory validation test environment that uses the underlying cache architecture for all caches in the memory subsystem hierarchy of a microprocessor system is presented. Tests are run from the main microprocessor(s) and use an algorithm for driving controlled data traffic on the local bus as well as the interconnect. Since the tests are runs from the main microprocessor(s), we are able to stress various code paths such as load store and invalidate queues where timing constraints may make a lot of difference at non-nominal physical and electrical conditions. To enhance the possibility of hitting faults sooner and easily, we use a mix of various kinds of memory patterns as input vectors, some random and some static, the static ones being derived from the performance modeling of various memory fault models.
© 2020 Vikas Chouhan